Author: Xiao Meng
As AI chips continue to evolve, Advanced Packaging has become a ubiquitous topic. TrendForce recently released a report assessing the competitive landscape of Advanced Packaging for AI chips. The report indicates that although solutions such as Intel's EMIB-T are vying for AI chip customers, TSMC's CoWoS-L is expected to remain the mainstream Advanced Packaging solution for AI chips through 2028, thanks to its technological maturity and yield advantages. This assessment implies that competition over AI chip packaging routes in the coming years will center on CoWoS-L; other solutions must demonstrate more compelling performance in terms of maturity and yield to penetrate this market.
01、Why Are AI Chip Packages Getting "Bigger"?
AI chips are becoming larger. However, this increase in size primarily refers to the package rather than the single compute die itself. As large model parameter scales and inference task complexity steadily improve, AI accelerators require higher computing power and greater memory bandwidth. A single chip struggles to independently meet all demands, making Chiplets and HBM critical means for enhancing system performance. The increasing amount of compute and storage resources required within the chip directly transfers pressure to the packaging stage.
NVIDIA's Rubin platform serves as an excellent example. According to public information, the Rubin GPU utilizes 336 billion transistors and features HBM4, with each GPU offering up to 288GB of VRAM and 22TB/s of memory bandwidth. AMD is also accelerating its iterations; the Instinct MI400 series adopts a Chiplet architecture, while the next-generation MI455X consists of 8 compute dies, targeting Helios rack-level systems composed of 72 GPUs. A common characteristic of these products is the increasing number of compute dies and HBM stacks integrated within a single package. In terms of package size, NVIDIA's Blackwell GPU has already reached approximately 3.3 times the reticle limit, and the next-generation Rubin platform is projected to reach 4 times.
As the number of compute dies and HBM stacks continues to rise, the traditional approach of a single chip plus external storage increasingly fails to meet AI systems' requirements for bandwidth and data transmission efficiency. Integrating more compute dies and HBM into the same Advanced Packaging shortens the data transmission distance between chips and provides greater bandwidth through high-density interconnects. Consequently, the "bigness" of AI chips ultimately manifests as an expansion in package size. What truly continues to grow is the total scale of compute dies, Chiplets, HBM, and high-speed interconnects that need to be integrated within a single Advanced Packaging unit, rather than just the lateral area of a single logic die.
Data shows that the expansion of package sizes has persisted for nearly a decade. According to IDTechEx's report on Advanced Packaging technology trends, the silicon interposer size of TSMC's CoWoS has evolved from approximately 1.5 times the reticle size (~1287mm²) in 2016 to the current 3.3 times (~2831mm²), with plans to expand to 5.5 times (~4719mm²) by 2026. The increase in package size is also directly reflected at the equipment level; HANMI Semiconductor's newly launched FC Bonder 75 supports package sizes of 75mm x 75mm, whereas traditional general-purpose package sizes are only 20mm x 20mm.
The forces driving larger packages are expanding from GPUs to AI ASICs. TrendForce data indicates that shipments of NVIDIA's high-end GPUs are expected to grow by approximately 30% year-over-year in 2026, while AMD is aggressively pushing MI400 and MI450 in the second half of 2026. Regarding CSP self-developed ASICs, Google shows the strongest shipment volume and momentum in 2026, with TPU v7 as the main product. AWS is gradually advancing Trainium v3 starting in the second half of the year, while Microsoft and Meta currently rely primarily on GPU Servers, with smaller planned volumes for ASICs. Different types of AI chips are evolving toward higher integration levels, implying that packages must continuously accommodate more compute and storage resources.
02、Why Do Package Sizes Encounter Bottlenecks?
As package sizes continue to expand, problems arise. Can such large interposers still be manufactured?
In traditional 2D packaging, chips are connected to the package substrate via bond wires, with metal traces and vias inside the substrate responsible for signal transmission. This path is long, introducing significant resistance and inductance, making signal latency and power consumption bottlenecks. When multiple chips are separately packaged and placed on a PCB, the physical distance for signals to transmit between them is quite long. To drive signals across this distance, power consumption increases significantly, thereby limiting the overall communication bandwidth between chips.
Area is another issue. Placing multiple large packages on a PCB occupies vast physical space, which is unacceptable for space-constrained products. More critically, there is a huge gap between the trace width on PCBs and the bumps/micro-bumps of chips. This disparity limits the number and density of I/Os, making traditional packaging methods difficult to satisfy the requirements of AI and High Performance Computing (HPC) for high bandwidth, low latency, and miniaturization. With limitations in interconnect length, physical area, and I/O density simultaneously, 2D packaging can no longer effectively support the integration needs of AI chips.
To address these issues, some vendors proposed 2.5D packaging solutions. The core idea involves introducing an interposer layer, placing multiple chips side-by-side on the interposer rather than directly on the PCB. Chips connect to the interposer via micro-bumps, and the interposer contains extremely fine Redistribution Layers (RDL) responsible for high-density, short-distance horizontal communication between chips. The interposer then connects vertically to the package substrate below via Through-Silicon Vias (TSVs). This approach drastically shortens the interconnect distance between chips, improving signal integrity and bandwidth, while bypassing the reticle limits that single chips cannot overcome, providing a viable path for integrating more compute dies and HBM in the future.
It is precisely along this 2.5D packaging path that TSMC's CoWoS has gradually become the representative solution.
03、CoWoS-L: The Mainstream 2.5D Solution
TSMC's CoWoS is a typical 2.5D packaging solution, whose core lies in integrating multiple SoCs or Chiplets with HBM within a single package.
Currently, TSMC's CoWoS family mainly includes three members: CoWoS-S, CoWoS-R, and CoWoS-L. The biggest difference among the three lies in the implementation method of the interposer. CoWoS-S uses a large-area silicon interposer, achieving high-density interconnects via routing on it to integrate logic chips and HBM together. CoWoS-R replaces the silicon interposer with RDL (Redistribution Layer). RDL consists of polymer and copper wiring layers, maintaining high interconnect performance while offering better mechanical flexibility, allowing easier scaling to support larger package sizes.
CoWoS-L merges the previous two approaches, representing a more flexible method. It bases routing on RDL while embedding small silicon pieces known as Local Silicon Interconnects (LSI). The "L" in CoWoS-L corresponds to Local Silicon Interconnect (LSI). TSMC states that LSI achieves high-routing-density die-to-die interconnects through multi-layer sub-micron copper lines, capable of handling SoC-to-SoC, SoC-to-Chiplet, and SoC-to-HBM connections according to different product needs. Meanwhile, RDL handles wider-range signal and power delivery. This way, high-density interconnects are concentrated in areas that truly require fine connections, rather than forcing the entire interposer to bear the same high-density routing.
This structural change is key to CoWoS-L's ability to further expand package sizes. For ultra-large-scale AI chips, not every area within the package requires the same high routing density. If all areas adopted the high-density routing method of silicon interposers, manufacturing costs and process complexity would increase synchronously with area expansion. By combining LSI and RDL, CoWoS-L applies high-density interconnects only where needed, utilizing RDL for broader connectivity and power delivery. Thus, it can further extend the overall package size while maintaining interconnect capabilities in critical areas. TSMC has already positioned CoWoS-L as a packaging solution supporting larger HPC products and continues to expand its interposer size to integrate more silicon chips and HBM.
This concept of local high density combined with large-area scaling also allows CoWoS-L to match well with the Chiplet architecture of AI chips. Future AI accelerators may simultaneously include multiple compute dies, Chiplets of different functions, and multiple HBM stacks, while data flows between different chips are not entirely identical. Some links require extremely high bandwidth and very short connection distances, while others focus more on regional signal and power distribution. CoWoS-L can configure interconnect structures for these different needs and can further integrate independent embedded Deep Trench Capacitors (eDTC) under the SoC to improve power management. In other words, packaging is beginning to shift from simply connecting chips to designing interconnects and power delivery for the entire computing system.
In terms of actual size evolution, CoWoS-L has moved out of the laboratory. TSMC's first 3.5x reticle-size CoWoS-L entered mass production in 2024. According to TSMC's public materials in 2025, the company completed certification of the 5.5x mask/reticle-size CoWoS solution and plans to start mass production in 2026 to meet the demand for higher performance from AI and HPC. TSMC also stated that it will continue to expand CoWoS interposer sizes to accommodate more advanced process nodes and HBM.
This technology route has also begun landing on the product side. TrendForce points out that AI accelerators from NVIDIA and AMD have already adopted CoWoS-L, and Meta's MTIA 400 also uses this packaging solution. As cloud service providers continue to develop self-designed ASICs, requiring the integration of more SoCs, Chiplets, and HBM within the same package, Microsoft and AWS are expected to adopt CoWoS-L in 2027. TrendForce believes that CoWoS-L, leveraging its technological maturity and yield advantages, is expected to remain the mainstream Advanced Packaging solution for AI chips until 2028.
However, CoWoS-L is not the only implementation path for 2.5D packaging.
04、EMIB: How Does Another Technology Route Progress?
If CoWoS-L focuses on the interposer, Intel's EMIB takes another 2.5D packaging route. EMIB stands for Embedded Multi-die Interconnect Bridge. Instead of using a large-area silicon interposer covering the entire package area, it embeds smaller silicon bridges into the package substrate, establishing connections only between chips that require high-density interconnects. Chips are still placed side-by-side on the substrate, but they can achieve high-density, high-speed data transmission between each other via the silicon bridges.
Compared to large-area silicon interposers, EMIB's approach is more localized. Silicon bridges appear only in areas where chips need high-speed communication, so there is no need to lay a complete silicon interposer across the entire package. Intel introduces that EMIB can customize bridge sizes and types for different die-to-die connections, establishing high-density interconnects between logic chips and logic chips, or logic chips and HBM, while avoiding routing all signals and power through a single block of silicon interposer. This improves interconnect density between different chips and allows for trade-offs between package structure and cost.
This structure is particularly suitable for Chiplet architectures. A single package can contain multiple dies from different process nodes and with different functions, bridged together via EMIB at various locations, forming a complete system with CPU, GPU, I/O, and HBM chips. Intel has already used EMIB in large-scale mass production and states that its assembly yield can reach levels close to those of traditional FCBGA packaging with comparable complexity.
However, EMIB has its own limitations. Since the silicon bridges are embedded in the package substrate rather than being a large-area silicon interposer covering the entire package, high-density connections between chips are ultimately still influenced by the substrate's routing capabilities. As HBM bandwidth continues to rise and data transmission volumes within AI chips increase, besides interconnect density, power delivery has also become a critical issue. For high-power AI chips, how to quickly and stably deliver sufficient current to the chips within limited package space, while reducing power noise and transmission loss, has become key to EMIB's further development.
EMIB-T emerged as an upgraded solution against this backdrop. The "T" corresponds to Through-Silicon Via (TSV). Intel added TSVs to the original local silicon bridges of EMIB, allowing power to be delivered vertically from the package substrate directly to the upper chips via the silicon bridge, without detouring through other routing layers. This shortens the power delivery path, increases power delivery density, and improves power integrity in high-power, high-bandwidth applications. Intel's public materials show that EMIB-T can also integrate multi-layer copper power/ground networks and high-density capacitors within the bridge, further reducing power network impedance and noise.
If EMIB is viewed as a bridge connecting chips, the biggest change in EMIB-T is adding a vertical channel to this bridge. Previously, it mainly solved how chips communicate; after adding TSVs, packaging can further solve how electricity is delivered directly upward. The EMIB-T solution showcased by Intel at ECTC 2026 has reduced the first-layer interconnect bump pitch to 25 microns, expanded the package size to 120mm×120mm, and supports the integration of compute and storage chips exceeding 9 reticle areas, while targeting high-speed interconnects such as 12 Gb/s HBM4e and 64 Gb/s UCIe.
This means EMIB is evolving from its initial local silicon bridge towards larger sizes, higher interconnect densities, and stronger power delivery capabilities. TrendForce notes that as CoWoS-L packaging costs and TSMC's Advanced Packaging capacity continue to draw attention, EMIB has become an alternative considered by some AI chip manufacturers. Google is expected to adopt EMIB-T in 2027, and AWS is testing EMIB technology. Although EMIB-T competes directly with CoWoS-L, CoWoS-L's advantages in technological maturity and yield are expected to keep it as the mainstream AI chip packaging technology until 2028. For Intel, EMIB-T not only expands package area but also enables local silicon bridges to handle both high-speed signals and vertical power delivery, providing a new packaging path for larger-scale AI chip integration.
05、From CoWoS-L to EMIB-T: How Will Advanced Packaging Move Forward?
Putting CoWoS-L and EMIB-T side by side reveals that the essence of their competition extends beyond packaging technology itself. Today, it is difficult for AI chips to gain performance solely by shrinking transistors; more and more compute dies, Chiplets, and HBM are integrated into the same package, and packaging itself is becoming part of chip design. CoWoS-L chooses to continue expanding the interposer, completing connections in different regions via RDL and Local Silicon Interconnects. EMIB-T advances along the embedded silicon bridge path. Although the routes differ, the goals are very close: both aim to enable more compute and storage resources to collaborate at high speed within a single package. Therefore, TrendForce judges that the competition for Advanced Packaging in AI chips in the coming years will still revolve around larger sizes and higher interconnect densities.
But as packages get bigger, 2.5D packaging itself begins to encounter increasing difficulties.
First, look at interconnects. The data exchange volume within AI chips has reached a point where simply adding compute units is insufficient; computed data must be delivered quickly to the next die and HBM. Distance, line width, and number of traces affect transmission speed and power consumption. Consequently, layout within the package and which chips should be placed closer together have begun to impact chip performance. Previously, packaging could be understood as the final step after chip manufacturing; now this statement is inaccurate. For Chiplet architectures, how dies are arranged and how interconnects are implemented must be considered together. The industry increasingly emphasizes package-level co-design, considering electrical, thermal, and mechanical issues simultaneously during chip design, packaging, and system design stages.
Thermal dissipation and yield are also unavoidable issues as 2.5D packaging continues. Current AI accelerators are high-power devices; the more chips placed in a package, the more concentrated the local heat. 2.5D can at least spread GPUs, ASICs, and HBM horizontally, leaving room for cooling, but horizontal space is ultimately limited.
Regarding yield, the value of a single AI chip is already high; now multiple compute dies, HBM, and extensive interconnect structures are integrated into one package. Any failure in any link can affect the entire package. As the number of chips increases, manufacturing, bonding, testing, and failure analysis require greater precision. Especially at the ultra-large package stage, the focus is not just on whether it can be made, but on whether it can be made stably while keeping costs down.
Given these dilemmas in 2.5D packaging, why not abandon it completely and switch to 3D packaging? Technically,3D packaging can certainly further improve integration density per unit area. TSMC's SoIC already supports 3D integration between logic chips and logic chips, or storage and logic chips, and 3nm SoIC stacking technology entered mass production in 2025. However, for high-power AI logic chips, large-scale 3D packaging still faces challenges in thermal dissipation, power delivery, and yield. Heat gets trapped within the stacked structure, power delivery must pass through more layers, and any layer failure can drag down the entire package. More critically,3D packaging is immature technically and economically; it requires multiple tape-outs and sets of masks, resulting in development and production costs far higher than traditional SoCs. Manufacturing processes are complex and yields are lower, further pushing up unit costs. Meanwhile, TSMC's CoWoS technology has achieved ten years of mass production with stable yields above 90%, whereas yield improvement in 3D packaging still relies on improvements in bonding precision. Currently, only a few technologically leading enterprises possess the capability to develop 3D packaging, and it is mainly applied in high-end markets insensitive to price. Therefore, 2.5D packaging remains more suitable as the mainstream path for large-scale AI chip integration at this stage.
Thus, the next round of competition in Advanced Packaging will not pursue package size alone. Size will certainly continue to grow, and interconnect density will continue to increase, but simultaneously, signal integrity, power integrity, thermal dissipation, yield, and cost will become issues that must be solved together. Chip manufacturers cannot wait until chip design is complete to decide on packaging; packaging capabilities likely need to participate from the very beginning of design. Looking further ahead, the development of HBM will continue to put pressure on packaging. Continuous increases in HBM capacity and bandwidth mean that a single AI package needs to carry more storage resources. Continued increases in compute dies will make data exchange between chips more frequent. The relationship between packaging, HBM, and compute chips will become increasingly tight, potentially leading to situations where chips are modified to fit packaging constraints.
06、Conclusion
CoWoS-L and EMIB-T are actually just two nodes in this wave of change. They solve the most practical problems arising from the rapid expansion of AI chip scale today. The real test for the industry chain in the next step is whether, after putting more chips together, they can still run fast, dissipate heat effectively, receive timely power, and maintain stable mass production. AI chips are continuing to get "bigger," and packaging can only move forward accordingly.
Where the next boundary will appear is worth our continued attention.