On October 30, the 31st meeting of the Second Board of Directors of Empyrean Technology (301269) unanimously approved a proposal to acquire no more than 51% equity in its invested company, Easy-Logic Technology, for an investment not exceeding CNY 220 million. Upon completion of the transaction, Easy-Logic Technology will become a controlled subsidiary and be included in the consolidated financial statements.
| Keyword: "Tau Scaling Law"
The announcement explained the purpose of the investment with an unusual statement: As Huawei's Tau Scaling Law is formally promoted for industrialization, along with chip process development, increasing design complexity, and continuously rising tape-out costs, the necessity and importance of logic optimization tools are becoming increasingly prominent. The terms "Tau Scaling Law" and "Tau Scenarios" appear twice in the announcement, and "supporting the industrialization of logic-folding chips" is explicitly stated as an investment objective.
What is the Tau Scaling Law? On May 25, 2026, He Tingbo, President of Huawei's Semiconductor Business Unit, proposed the τ Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS 2026), advocating for "temporal scaling" to replace "geometric scaling"—as the marginal returns from process miniaturization diminish, the focus of innovation shifts from "making transistors smaller" to "making signals run faster." Its core technology is "Logic Folding": rather than simply stacking several chips together, it reconstructs logical layouts from a three-dimensional perspective at the initial design stage, distributing circuits to more appropriate positions, and co-designing multiple Dies as a single complete chip, thereby shortening routing, reducing RC load, and compressing signal propagation delay τ.
This path has moved beyond the laboratory. The Kirin 9050 series is the first logic-folding chip; public data shows that its transistor density increased by approximately 53.5%, hybrid bonding counts exceeded 50 million, NPU performance improved by 140% while power consumption decreased by 66%, and CPU multi-core performance increased by 23%. Huawei states that there remains room for continuous evolution in logic folding over the next decade, with multi-layer folding being one direction.
The critical juncture lies here: Logic folding changes the organizational method of circuits, and EDA tools are the executors of these organizational methods. Three-dimensional logical reconstruction, cross-Die collaborative optimization, and joint convergence of timing and power—these fall precisely within the domains of logic synthesis and logic optimization, which is where Easy-Logic Technology operates. Huang Yu, Chief Scientist of Huawei Semiconductor EDA, stated frankly at the 2026 Greater Bay Area Chip Exhibition, "The greatest challenge of the Tau Scaling Law lies in EDA tools."
This explains why Empyrean Technology wrote the Tau Scaling Law into the investment objectives in the announcement. Most interpretations stop at "filling gaps in digital EDA," but the announcement's focus is clearer: it is not about filling a generic process step, but about preparing tools in advance for a chip paradigm that has already begun mass production. If logic folding extends from smartphones to more chip categories as Huawei plans, digital backend optimization capability becomes the entry ticket.
| Where Does Logic Optimization Get Stuck?
The chain of digital circuit design is: Logic Synthesis → Logic Optimization → Place & Route → Timing Analysis and Verification.
The announcement defines its value as follows: "Under the premise of ensuring design quality, minimizing the time and resource consumption of design iterations is an important guarantee for successful chip tape-out and commercialization."
Translated into cost language: If the quality of the synthesized netlist is insufficient, subsequent rework is required repeatedly, with each iteration consuming both schedule and computing power. The value of the tool does not lie in the length of its feature list, but in reducing the number of process rounds. This is also why the announcement juxtaposes "increasing design complexity" with "continuously rising tape-out costs"—the more expensive the tape-out, the more money saved by avoiding even one iteration, and this is the foundation upon which logic optimization can command a price.
| Analog Fully Connected, Digital Still Lacking 20%
Empyrean Technology develops EDA tools covering design, manufacturing, and packaging. Its base business is full-flow support for full-custom designs—covering analog, memory, RF, and flat panel display directions, all forming systematic solutions, with market share consistently ranking first among domestic EDA companies.
The digital side presents a different situation: After nearly two years of intensive supplementation, the product variety of Empyrean's digital circuit design EDA covers approximately 80% of major digital design tools, still lacking the final segment to achieve a "full flow." What is missing? Steps like logic synthesis, place & route, and logic optimization, which serve as bridges between stages, are precisely the deepest and most difficult positions to bypass held by the international big three.
Looking at its current status reveals why they chose to "buy" rather than "develop internally": In the first half of2026, revenue was CNY 566 million, up 12.95% year-on-year, but R&D expenses were CNY 411 million, accounting for 72.61% of revenue, putting pressure on net profit (net profit attributable to parent company shareholders: -CNY 45.0634 million). A company investing 70% of its revenue into R&D faces too high a time cost to catch up on an algorithm-intensive segment through self-research. Revenue for the first three quarters was CNY 960 million, up 19.30% year-on-year; net profit attributable to parent company shareholders for the third quarter alone was CNY 71.9981 million, showing significant improvement in profitability. However, net profit attributable to parent company shareholders for the first three quarters was only CNY 26.9347 million, and non-recurring items adjusted net profit was -CNY 30.9542 million, meaning the adjusted metric has not yet turned positive—to be precise, the operational aspect is experiencing marginal recovery rather than comprehensive recovery. There is capital, and there is necessity; acquisition buys time.
Another detail worth noting: Empyrean Technology is one of the few domestic EDA vendors with full-flow capabilities for 3DIC design verification. This means their judgment on the 3DIC path is not theoretical speculation but based on having tools in hand and observing how customers use them.
| Fundamentals of the Target
Easy-Logic Technology was established on January 15, 2021, with registered capital of CNY 2.34315966 million, registered in Futian, Shenzhen, with legal representative Wei Xing. It focuses on the R&D and sales of logic optimization EDA tools. Its products have been adopted by nearly 100 digital chip design companies domestically and internationally. It has R&D centers in Shenzhen, Shanghai, Beijing, and Hong Kong, and has been recognized as ISO9001 certified, a Specialized, Refined, Distinctive, and Innovative SME, a National High-Tech Enterprise, and a Seed Unicorn.
Financials remain in loss: In 2025, revenue was CNY 32.2504 million, net profit -CNY 19.3865 million; from January to September 2026, revenue was CNY 27.4225 million, net profit -CNY 5.9065 million. As of September 30, 2026, net assets were CNY 29.0592 million.
However, customer count is more worthy of attention than profit initially: Five years since establishment, adoption by nearly 100 companies—for a tool company, customer penetration often precedes profitability.
| Three Reasons for Investment
First reason in the announcement: The investment "not only fills the gap in digital logic optimization design tools but also, after integrating Easy-Logic Technology's products, helps build next-generation AI/3DIC digital design logic and performance optimization solutions."
The logic chain is robust: Process evolution → Increased design complexity → Rising tape-out costs → Amplified iteration penalties → Logic optimization shifts from optional to essential. Moreover, 3DIC brings changes in coupling relationships, where timing, power, and heat intertwine, increasing complexity multiplicatively rather than additively, making trial-and-error based on human experience unsustainable. This is precisely why the announcement directly links Easy-Logic's technical reserves with the "industrialization of logic-folding chips."
The second reason is talent, with key wording: The announcement states "introducing a structured R&D team," mentioning that its members have won world championships in international EDA algorithm competitions multiple times. "Structured" implies the migration of a complete team rather than piecemeal poaching—in an algorithm-intensive industry, this is harder to obtain than a single product.
The third reason is often overlooked but represents the other half of the objective: "Adding new momentum to revenue growth," focusing on building innovative EDA solutions for Tau scenarios and expanding application market space. Beyond filling gaps, this acquisition also lays groundwork for the next phase of revenue structure.
| Conclusion
The competition of single-point tools in domestic EDA is nearing its end; customers buy whether the entire flow can run smoothly. One less break in the flow means one less rework.
CNY 219 million is not buying current-period revenue, but a puzzle piece in the flow. Whether it can truly fit into the existing system and transform "logic folding" and AI/3DIC from concepts into deliverable tools depends on subsequent integration and customer validation. But this puzzle piece is positioned in the hardest and most valuable slot of digital EDA.
Disclaimer: This article is compiled based on Empyrean Technology's public announcements (2026-055, 2026-056) and publicly disclosed information, intended solely for reference and research exchange, and does not constitute any investment advice. The transactions mentioned herein require final agreement signing by all parties; specifics are subject to company announcements; relevant data are subject to official disclosure documents of listed companies. Investors act at their own risk.
Editor: Shuo Xin Yu - Xiao Ming Ba